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Preliminary Technical Data
FEATURES
Yaw rate gyro with digital range scaling 80/sec, 160/sec, and 320/sec settings 14-bit digital gyroscope sensor outputs 12-bit digital temperature sensor output Calibrated sensitivity and bias In-system, auto-zero for bias drift calibration Digitally controlled sample rate Digitally controlled frequency response Dual alarm settings with rate/threshold limits On-board integration for short-term angle estimates Digitally activated self-test Digitally activated low power mode Interrupt-driven wake-up SPI(R)-compatible serial interface Auxiliary 12-bit ADC input and 12-bit DAC output Auxiliary digital input/output Single-supply operation: 4.75 V to 5.25 V 2000 g powered shock survivability
Programmable Low Power Gyroscope ADIS16250
FUNCTIONAL BLOCK DIAGRAM
AUX ADC AUX DAC VREF
ADIS16250
TEMPERATURE SENSOR
RATE FILT
GYROSCOPE SENSOR
CS SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING SCLK SPI PORT DIN DOUT
SELF-TEST
DIGITAL CONTROL
VCC POWER MANAGEMENT COM ALARM AUXILIARY I/O
RST
DIO0
DIO1
05462-001
Figure 1.
APPLICATIONS
Instrumentation control Platform control and stabilization Motion control and analysis Avionics instrumentation Navigation Image stabilization Robotics
GENERAL DESCRIPTION
The ADIS16250 is a complete, angular rate measurement system available in a single compact package enabled by Analog Devices' iSensorTM integration. By enhancing Analog Devices' iMEMS(R) sensor technology with an embedded signal processing solution, the ADIS16250 provides factory calibrated and tunable digital sensor data in a convenient format that can be accessed using a simple SPI serial interface. The SPI interface provides access to measurements for the gyroscope, temperature, power supply, and one auxiliary analog input. Easy access to calibrated digital sensor data provides developers with a systemready device, reducing development time, cost, and program risk. The device range can be digitally selected from three different settings: 80/sec, 160/sec, and 320/sec. Unique characteristics of the end system are accommodated easily
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
through several built-in features, including an auto-zero recalibration via a single register command, as well as configurable sample rate and frequency response. Additional features can be used to further reduce system complexity, including a configurable alarm function, an auxiliary 12-bit ADC, an auxiliary 12-bit DAC, a configurable digital I/O port, and a digital self-test function. System power dissipation can be optimized via the ADIS16250 power management features, including an interrupt-driven wake-up. The ADIS16250 is available in an 11 mm x 11 mm x 5.5 mm laminate-based land grid array (LGA) package with a temperature range of -40C to +85C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADIS16250 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Theory of Operation ........................................................................ 8 Overview........................................................................................ 8 Basic Operation ............................................................................ 8 Register Details ............................................................................. 8 Calibration................................................................................... 11 Range Selection........................................................................... 11 Relative Angle Estimate ............................................................. 11 Control Register Operation........................................................... 12 Overview...................................................................................... 12 Access ........................................................................................... 12 Alarms.......................................................................................... 13 General Purpose I/O Control ................................................... 14
Preliminary Technical Data
Miscellaneous Control Register................................................ 14 Sample Period Control .............................................................. 14 Sensitivity/Filtering Control ..................................................... 14 Power-Down Control ................................................................ 15 Status Feedback........................................................................... 15 Command Control..................................................................... 15 Peripherals ....................................................................................... 16 Auxiliary ADC Function........................................................... 16 Auxiliary DAC Function ........................................................... 16 Register Details ............................................................................... 17 Data Output Register Definitions ............................................ 17 Calibration Register Definitions .............................................. 17 Alarm Register Definitions ....................................................... 18 Programable Feature Register Definitions.............................. 19 Applications..................................................................................... 23 Hardware Considerations ......................................................... 23 Grounding and Board Layout Recomendations .................... 23 Bandgap Reference..................................................................... 23 Second-Level Assembly ............................................................. 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
Rev. PrB | Page 2 of 28
Preliminary Technical Data SPECIFICATIONS
TA = -40C to +85C, VCC = 5.0 V, angular rate = 0/sec, 1 g, unless otherwise noted. Table 1.
Parameter SENSITIVITY Dynamic Range 1 Initial 2 Conditions Clockwise rotation is positive output Full-scale range At 25C, dynamic range = 320/sec At 25C, dynamic range = 160/sec At 25C, dynamic range = 80/sec VCC = 4.75 V to 5.25 V Best fit straight line Min 320 13.65 27.3 54.6 TBD 0.1 1.0 TBD 150 TBD TBD 0.5 0.3 0.15 0.05 50 14 +32 -32 +53 -53 0 +6.88 12 2 1 4 2 0 During acquisition At 25C -10 40 70 5 k/100 pF to GND For Code 101 to Code 4095 12 4 1 5 0.5 0 to 2.5 20 2.5 +10 2.5 +80 -80 Typ
ADIS16250
Max
Unit /sec LSB//sec LSB//sec LSB//sec ppm//sec % of FS /sec ppm/C ms /sec/g /sec/V /sec rms /sec rms /sec rms /sec/Hz rms Hz kHz /sec /sec LSB LSB/C Bits LSB LSB LSB LSB V pF V mV ppm/oK Bits LSB LSB mV % V
Temperature Drift Nonlinearity NULL Initial Null Temperature Drift Turn-On Time Linear Acceleration Effect Voltage Sensitivity NOISE PERFORMANCE Output Noise
VCC = 4.75 V to 5.25 V Power on to 2/sec of final, no averaging, minimum sample period Any axis VCC = 4.75 V to 5.25 V, max averaging At 25C, 320/sec dynamic range, no filtering At 25C, 160/sec dynamic range, 4-tap filter At 25C, 80/sec dynamic range, 16-tap filter At 25C, f = 25 Hz, no average 0 nF as comp cap (see Setting Bandwidth)
Rate Noise Density FREQUENCY RESPONSE 3 dB Bandwidth (User Selectable) Sensor Resonant Frequency SELF-TEST STATE Change for Positive Stimulus Change for Negative Stimulus TEMPERATURE SENSOR Output at 25C Scale Factor ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range
Relative to nominal output Relative to nominal output
Rev. PrB | Page 3 of 28
ADIS16250
Parameter Output Impedance Output Settling Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period 3 FLASH MEMORY Endurance 4 Data Retention 5 CONVERSION RATE Minimum Conversion Time Maximum Conversion Time Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range VCC Power Supply Current Conditions
Preliminary Technical Data
Min Typ 2 10 Max Unit s V V V A A pF V V Sec Cycles Years 3.906 7.75 250 0.129 4.75 Normal mode at 25C Fast mode at 25C Sleep mode at 25C 5.0 15 41 500 5.25 19 48 750 ms Sec SPS SPS V mA mA A
2.0 For -CS signal when used to wake up from SLEEP mode VIH = 3.3 V VIL = 0 V 0.8 0.55 10 -60
0.2 -40 10 2.4
ISOURCE = 1.6 mA ISINK = 1.6 mA
0.4 0.5 20,000 20 128
TJ = 55C
1 2 3
Dynamic range is only limited by performance criteria; sensor structure is capable of measuring +600/sec with degraded performance. Dynamic range setting can be established by accessing the SENS/AVG register. Guaranteed by design. 4 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +125C. 5 Retention lifetime equivalent at junction temperature (TJ) 55C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.
Rev. PrB | Page 4 of 28
Preliminary Technical Data
TIMING SPECIFICATIONS
TA = -40C to +85C, VCC = 5.0 V, unless otherwise noted. Table 2.
Parameter fSCLK tDATARATE tDATARATE tcs tDAV tDSU tDHD tDF tDR tSFS
1 2
ADIS16250
Description Fast Mode 2 Normal Mode2 Chip Select Period, Fast Mode Chip Select Period, Normal Mode Chip Select to Clock Edge Data Output Valid after SCLK Edge Data Input Setup Time Before SCLK Rising Edge Data Input Hold Time After SCLK Rising Edge Data Output Fall Time Data Output Rise Time CS High after SCLK Edge
Min 1 0.01 0.01 40 100 48.8 24.4 48.8
Typ
Max1 2.5 1.0
100
5 5 5
12.5 12.5
Unit MHz MHz s s ns ns ns ns ns min ns min ns typ
Guaranteed by design, typical specifications are not tested or guaranteed. Based upon sample rate selection.
tDATA RATE tSTALL
CS
05462-002
SCLK
Figure 2. SPI Chip Select Timing
CS
tCS
1 SCLK 2 3 4 5 6 15 16
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN W/R A5
tDHD
A4 A3 A2 D2 D1 LSB
05462-003
Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. PrB | Page 5 of 28
ADIS16250 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) VCC to COM Digital Input/Output Voltage to COM Analog Inputs to COM Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g -0.3 V to +6.0 V -0.3 V to +5.5 V -0.3 V to 3.5 V -40C to +85C -65C to +150C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 6 of 28
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16250
DNC - DO NOT CONNECT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5, 6 7 8, 9 10, 11 12 13 14 15 16,17 18,19 20
1
Mnemonic SCLK DOUT DIN CS DIO0, DIO1 RST DNC AUX COM AUX DAC AUX ADC RATE FILT VCC COM VREF
Type 1 I O I I I/O I - I O I O I S S O
Description Serial Clock. SCLK provides the serial clock for accessing data from the part and writing serial data to the control registers. Data Out. The data on this pin represents data being read from the control registers and is clocked out on the falling edge of the SCLK. Data In. Data written to the control registers is provided on this input and is clocked in on the rising edge of the SCLK. Chip Select, Active Low. This input frames the serial data transfer. Multifunction Digital Input/Output pin. Reset, Active Low. This resets the sensor signal conditioning circuit and initiates a start-up sequence. Do Not Connect. Auxiliary Grounds. Connect to GND for proper operation. Auxiliary DAC Analog Voltage Output. Auxiliary ADC Analog Input Voltage. Analog Rate Signal Output. Analog Amplifier Summing Junction. +5.0 V Power Supply. Common. Reference point for all circuitry in the ADIS16250. Precision Reference Output.
S = Supply; O = Output; I = Input.
Rev. PrB | Page 7 of 28
ADIS16250 THEORY OF OPERATION
OVERVIEW
The core angular rate sensor integrated inside the ADIS16250 is based on Analog Devices' iMEMS technology. This sensor operates on the principle of a resonator gyro. Two polysilicon sensing structures each contain a dither frame, which is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force during angular rate. At two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers that are placed between fixed pickoff fingers to form a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The base sensor's output is sampled using an ADC and then the digital data is fed into a proprietary digital calibration circuit. This circuit contains calibration coefficients from the factory calibration, along with user-defined calibrations that can be used to calibrate system-level errors. The calibrated gyro data is made available through output data registers along with temperature, power supply, auxiliary ADC, and relative angle output calculations.
Preliminary Technical Data
writing to a set of registers that have been dedicated to the required I/O functions. These registers are accessed by using the 4-wire, serial peripheral interface (SPI) port. Each one has its own unique address and bit assignments that have been optimized for each function. The output data registers are summarized in Table 6. The control registers are summarized in Table 9. Using the ADIS16250 in the most basic, simple configuration requires only the power supply connections (+5 V/COM) and the SPI port's four wires. A common approach for accessing the ADIS16250 through the SPI port is with a digital processing solution, such as the Blackfin(R) family of DSP/MCUs. For example, the BF533 has seven different SPI ports that can each be used to access multiple SPI-driven devices.
REGISTER DETAILS
The registers in the ADIS16250 are 16 bits in length. Each of them has been assigned an address for their upper byte and lower byte. Each control register's bit map uses the numerical assignments that are displayed in Table 5. Table 5. Basic Register Bit Map
MSB 15 7 14 6 13 5 12 4 11 3 10 2 9 1 LSB 8 0
BASIC OPERATION
The ADIS16250 is a calibrated, digital angular rate sensor that also provides power supply measurements, temperature measurements, auxiliary ADC data, and integrated angular rate data. It also offers a number of useful programmable features that allow users to optimize its operation in their systems. The basic operation of the ADIS16250 is facilitated by reading and
The upper byte consists of Bit 8 to Bit 15, and the lower byte consists of Bit 0 to Bit 7. The following sections provide descriptions of each register including purpose, scaling information, bit maps, addresses, and default values.
Table 6. Data Output Register Information
Name SUPPLY_OUT GYRO_OUT AUX_ADC TEMP_OUT ANGL_OUT
1
Function Power Supply Data Gyroscope Data Auxiliary Analog Input Data Sensor Temperature Data Angle Output
Address 0x03, 0x02 0x05, 0x04 0x0B, 0x0A 0x0D, 0x0C 0x0F, 0x0E
Resolution (Bits) 12 14 12 12 14
Data Format Binary Twos Complement Binary Binary Binary
Scale Factor (per LSB) 1.22 mV 0.07326/sec 1 0.61 mV -0.47C 0.03663
Assumes that the scaling is set to 320/sec.
Rev. PrB | Page 8 of 28
Preliminary Technical Data
SPI Operation
The ADIS16250 SPI port provides full duplex data transfer, which maximizes the efficiency of each data transfer. By using a single SCLK edge to accomplish both data input reads (DIN) and data output transfers (DOUT), ADIS16250 data transfers require less of the serial buses' time. Each data transfer is 16 SCLK cycles in length. Read cycles require two data transfer cycles while write cycles only require one. The 4-wire SPI port lines are assigned as follows: the chip select line (~CS), the data clock (SCLK), data input (DIN), and data output (DOUT).
ADIS16250
contents of the register have been written since the last read cycle. Otherwise, the contents of the register have previously been read. If the condition of the EA bit is a Logic 1, an error or alarm condition occurs, announcing the need to read the STATUS register. The angular rate data and angle out data registers are 14 bits in length. The angular rate data is formatted as a two's complement number and the angle output is formatted as binary data. The rest of the data output registers are 12 bits in length, leaving D12 and D13 as "don't care" bits. The output format for each of these registers, along with their addresses, can be found in Table 6. Each output data register has two different addresses. The first address is for the upper byte, which contains the most significant bits (D8 to D13), ND, and EA data. The second address is for the lower byte, which contains the eight least significant bits (D0 to D7). Reading either of these addresses results in all 16 bits being clocked out on the DOUT line as defined in Figure 5 during the next SPI cycle.
Reading Registers
Reading the contents of any accessible register in the ADIS16250 requires two data transfer cycles: one for transferring the register's address and one for reading the two bytes from the register. Figure 5 displays the sequence of a read cycle on the ADIS16250 SPI port and Table 8 contains the bit definitions for DIN and DOUT. The DIN sequence starts with two zeros, followed by the registers address, A5 to A0. For example, the GYRO_OUT register address is 0x04, which results in an A5 to A0 bit sequence of 000100. The last 8 bits in the DIN sequence, B7 to B0, are ignored by the ADIS16250 during read cycles. During the next data transfer cycle, the 16bit contents of the register are read out on the DOUT pin, starting with two status bits, new data (ND) and error/alarm (EA). Then, the data associated with the GYRO_OUT register are transferred out, starting with the MSB. The ND bit provides the ability to check if a conversion cycle has been complete. If the ND bits condition is a Logic 1, the Table 7. Output Coding Example, GYRO_OUT 1, 2
320/sec range +600/sec +320/sec +80/sec +40/sec +0.07326/sec 0/sec -0.07326/sec -40/sec -80/sec -320/sec +600/sec
1 2
Writing to Registers
Write cycles require one 16-SLCK data transfer cycle. Once the ~CS line is taken low, the information on DIN is clocked in using the next 16 SLCK cycles. The first bit in the DIN sequence is a 1, which identifies the write designation. The second bit is a 0, which is followed by 6 bits that identify the address of the register being written to. The last 8 bits contain the contents that are to be written to the register. Because all of the registers are 2 bytes in length, a complete register update takes two 16SCLK cycles.
Rate of Rotation 160/sec range +300/sec +160/sec +40/sec +20/sec +0.03663/sec 0/sec -0.03663/sec -20/sec -40/sec -160/sec -300/sec
80/sec range +150/sec +80/sec +20/sec +10/sec +0.018315/sec 0/sec -0.018315/sec -10/sec -20/sec -80/sec -150/sec
Binary Output 01 1111 1111 1111 01 0001 0001 0001 00 0100 0100 0100 00 0010 0010 0010 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1101 1101 1110 11 1011 1011 1100 10 1110 1111 0000 10 0000 0000 0000
HEX Output 0x1FFF 0x1110 0x0444 0x0222 0x0001 0x0000 0x3FFF 0x3DDE 0x3BBC 0x2EF0 0x2000
Decimal 8191 4368 1092 546 1 0 -1 -546 -1092 -4368 -8192
Two MSBs have been masked off and are not considered in the coding. Nominal sensitivity and zero offset null performance are assumed.
Rev. PrB | Page 9 of 28
ADIS16250
CS
Preliminary Technical Data
SCLK
DIN W/R bit
ADDRESS Zero
DATA/IDLE
NEXT COMMAND
DOUT
BASED ON PREVIOUS COMMAND
16-BIT DATA WORD
Figure 5. Register Read/Write Command Sequence
Table 8. Register Read/Write Command Bit Map
DIN DOUT W/R 0 A5 D13 A4 D12 A3 D11 A2 D10 A1 D9 A0 D8 B7 B6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0
ND EA Upper Byte
D7 D6 Lower Byte
Rev. PrB | Page 10 of 28
Preliminary Technical Data
CALIBRATION
The ADIS16250 angular rate output is calibrated at the factory, providing a high degree of accuracy and simpler system implementation. In addition, for system or field updates, the device has two control registers associated with calibrating the angular rate output data (see the Calibration Register Definitions section). Each of these registers has read/write capability and is 16 bits (2 bytes) in length. The calibration factors are 12 bits in length. The GYRO_OFF register uses the twos complement format allowing for both positive and negative offsets. The GYRO_SCALE register uses a straight binary format. The data within these two calibration registers is utilized in offsetting and scaling of the output data registers according to the following relationship:
ADIS16250
A global command is implemented within the ADIS16250 to simplify the loading of the GYRO_OFF register. Once the device is no longer rotating, establishing a zero-reference rotation, a null command can be sent to the ADIS16250 via the command control register, which zeros the GYRO_OUT and ANGL_OUT registers. Consequently, on the next reading of the five output data registers, the angular rate output should be set to zero. (neglecting noise and repeatability limitations). It is suggested that when the null command is implemented, the AVG_CNT control register be adjusted to optimize the filtering and reduce the effects of noise in determining the values to be loaded into the offset control registers. Optionally, the user can manually load each of the two calibration registers via the SPI in order to calibrate the end system. This is applicable when the user plans to adjust the scale factor, thus requiring an external stimulus to excite the ADIS16250.
Output = A x ( x + C )
where: x represents the raw data prior to calibration. C is the offset. A is the scalar. Output represents the output data register where the resultant data is stored. Simple access to these registers enables field calibration to correct for in-system error sources. In particular, the GYRO_OFF register allows the user to reset to 0/sec reference point for the device. The GYRO_SCALE register allows for adjusting the sensitivity of the sensor measurements.
RANGE SELECTION
The AD16250 offers three different measurement ranges: 320/sec, 160/sec, and 80/sec. The maximum sample rate for each of these settings is 256, 64, and 16 samples per second respectively.
RELATIVE ANGLE ESTIMATE
The ANGL_OUT register offers the integration of the GYRO_OUT data. This number is reset when the NULL command is used, after a RESET command is used, and during power-up. This function can be used to estimate change in angle over a period. Users are cautioned to fully understand their stability requirements and the time period over which they can use this estimate relative angle position.
Rev. PrB | Page 11 of 28
ADIS16250 CONTROL REGISTER OPERATION
OVERVIEW
The Theory of Operation section describes the most basic operation of the ADIS16250. For added system flexibility and programmability, the following sections describe additional controls for the ADIS16250 sensor, as provided by the use of 21 digital control registers accessible via the SPI interface. A high level listing of these registers is given within Table 9. This table also refers to the appropriate tables regarding each register's definition. The following sections expand upon the functionality of each of these control registers, providing for the full clarification of each of the control registers behavior. Available control modes for the device include selectable sample rates for reading the five output vectors, selectable data averaging at the output registers, alarm settings, control of the on-board 12-bit auxiliary DAC, handling of the two general purpose I/O lines, facilitating of the sleep mode, enabling the self-test mode, and other miscellaneous control functions. The conversion process is repeated continually, providing for the continuous update of the five output registers. New data ready bit (ND) flag bits common to all five output registers allow the completion of the conversion process to be tracked via the SPI. As an alternative, the digital I/O lines can be configured through software control to create a data ready hardware function that can signal the completion of the conversion process. Two independent alarms provide the ability to monitor any one of the five output registers. They can be configured to report an alarm condition on either fixed thresholds or rates of change. The alarm conditions are monitored through the SPI. In addition, the user can configure the digital I/O lines through software control to create an alarm function that allows for monitoring of the alarm conditions through hardware. The five output signals noted above are calibrated independently at the factory, delivering a high degree of accuracy. In addition, the user has access to independent offset and scale factors for the gyroscope output vector. This allows independent scaling and level adjustment control of gyroscope register prior to the value being read via the SPI. In turn, field level calibrations can be implemented within the sensor itself using these offset and scale variables. System level commands provided within the sensor include automatic zeroing of the gyroscope output and the angle output using a single null command via the SPI. In addition, the original factory calibration settings can be recovered at any point using a simple factory reset command.
Preliminary Technical Data
ACCESS
The control registers within the ADIS16250 are based upon a 16-bit/2-byte format, and are accessed via the SPI. The SPI operates in full duplex mode with the data clocked out of the DOUT pin at the same time data is clocked in through the DIN pin. All commands written to the ASIS16250 are categorized as write commands or read commands. All write commands are self-contained and take place within a single cycle. Each read command requires two cycles to complete; the first cycle is for transmitting the register address and the second cycle is for reading the data. During the second cycle, when the data out line is active, the data in line is used to receive the next sequential command; this allows for overlapping the commands. For more information on basic SPI port operation, see the SPI Operation section. The read and write commands are identified through the most significant bit (MSB), B15, of the received data. Write a 1 to B15 to indicate a write command. Write a 0 to B15 to indicate a read command. Bit B13 through Bit B8 contain the address of the control register that is being accessed. The remaining 8 bits of the write command contain the data that is being written into the part, whereas the remaining 8 bits of the read command contain "don't care" levels. Given that the data within the write command is 8 bits in length, the 8-bit data format is the default byte size. A write command operates on a single chip select cycle as shown in Figure 5. The read command operates on a 2-chip select cycle basis as seen in Figure 5. All 64 bytes of register space is accessed using the 6-bit address. Data written into the device is performed on a byte-wise basis with the address of each byte being explicitly called out in the write command. Conversely, data being read from the device consists of two, back-to-back, 8-bit variables being sent out with the first byte out corresponding to the upper address (odd number address) and the second byte relating to the next lower address space (even number address). For example, a data read of address 0x03 results in the data from address 0x03 being fed out followed by data from address 0x02. Likewise, a data read of address 0x02 results in the same data stream being output from the device The ADIS16250 is a flash-based device with nonvolatile functional registers implemented as flash registers. Take into account the endurance limitation of 20,000 writes when considering the system-level integration of these devices. The nonvolatile column in Table 9 indicates which registers are recovered upon power-up. The user must instigate a manual flash update command via the command register to store the nonvolatile data registers once they are configured properly. When performing a manual flash update command, the user needs to assure that the power supply remains within limits for a minimum of 50 s after the write is initiated. This assures a successful write of the nonvolatile data.
Rev. PrB | Page 12 of 28
Preliminary Technical Data
Table 9. Control Register Mapping
Register Name SUPPLY_OUT GYRO_OUT AUX_ADC TEMP_OUT ANGL_OUT GYRO_OFF GYRO_SCALE ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD SENS/AVG PWR_MDE STATUS COMMAND Type R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Address 0x02 0x04 0x06 to 0x09 0x0A 0x0C 0x0E 0x10 0x14 0x16 0x18 to to 0x1F 0x20 0x22 0x24 0x26 0x28 0x2A to 0x2F 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E Bytes 2 2 4 2 2 2 4 2 2 8 2 2 2 2 2 6 2 2 2 2 2 2 2 2 Function Power Supply Output Data. X-Axis Gyroscope Output Data. Reserved. Auxiliary ADC Data. Temperature Output Data. X-Axis Angular Output Data. Reserved. Gyroscope Offset Factor. Gyroscope Scale Factor Reserved. Alarm 1 Amplitude Threshold. Alarm 2 Amplitude Threshold. Alarm 1 Sample Period. Alarm 2 Sample Period. Alarm Source Control Register. Reserved. Auxiliary DAC Data. Auxiliary Digital I/O Control Register. Miscellaneous Control Register. ADC Sample Period Control. Defines both sensitivity setting and the number of taps selected for the digital filter. Counter used to determine length of power-down mode. System Status Register. System Command Register.
ADIS16250
Reference Table Table 10, Table 11 Table 12, Table 13 Table 14,Table 15 Table 16, Table 17 Table 18, Table 19 Table 20, Table 21 Table 22, Table 23 Table 24, Table 25 Table 28, Table 29 Table 26, Table 27 Table 30, Table 31 Table 32, Table 33 Table 48, Table 49 Table 46, Table 47 Table 44, Table 45 Table 34, Table 35 Table 36, Table 37
Table 40, Table 41 Table 42, Table 43
ALARMS
The ADIS16250 contains two independent alarm functions that are referred to as Alarm 1 and Alarm 2. The Alarm 1 function is managed by the ALM_MAG1 and ALM_SMPL1 control registers. The Alarm 2 function is managed by the ALM_MAG2 and ALM_SMPL2 control registers. Both the Alarm 1 and Alarm 2 functions share the ALM_CTRL register. For simplicity, the following text references the Alarm 1 functionality only. The 16-bit ALM_CTRL register serves three distinct roles in controlling the Alarm 1 function. First, it is used to enable the overall Alarm 1 function and select the output data variable that is to be monitored for the alarm condition. Second, it is used to select whether the Alarm 1 function is based upon a predefined threshold (THR) level or a predefined rate-of-change (ROC) slope. Third, the ALM_CTRL register can be used in setting up one of the two general-purpose input/output lines (GPIOs) to serve as a hardware output that indicates when an alarm condition has occurred. Enabling the I/O alarm function, setting its polarity, and controlling its operation are accomplished using this register. Note that when enabled, the hardware output indicator serves both the Alarm 1 and Alarm 2 functions and cannot be used to differentiate between one alarm condition and the other. It is
simply used to indicate that an alarm is active and that the user should poll the device via the SPI to determine the source of the alarm condition (see Table 40). Because the ALM_CTRL, MSC_CTRL, and GPIO_CTRL control registers can influence the same GPIO pins, a priority level has been established to avoid conflicting assignments of the two GPIO pins. This priority level is defined as MSC_CTRL, which, in turn, has precedence over ALM_CTRL, which has precedence over GPIO_CTRL. The ALM_MAG1 control register used in controlling the Alarm 1 function has two roles. The first role is to store the value with which the output data variable is compared to discern if an alarm condition exists or not. The second role is to identify whether the alarm should be active for excursions above or below the alarm limit. The comparison value contained within the ALM_MAG1 control register is located within the lower 14 bits. The format utilized for this 14-bit value should match that of the output data register that is being monitored for the alarm condition. For instance, if the GYRO_OUT output data register is being monitored by Alarm 1, then the 14-bit value within the ALM_MAG1 control register takes on a twos complement format with each LSB equating to nominal 0.07326/sec
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ADIS16250
(assumes unity scale and zero offset factors). The ALM_MAG value can be compared against the filtered or unfiltered data of the parameter being monitored. Use caution when monitoring the temperature output register for the alarm conditions. Here, the negative temperature scale factor results in the greater than and less than selections requiring reverse logic. When the THR function is enabled, the output data variable is compared against the ALM_MAG1 level. When the ROC function is enabled, the comparison of the output data variable is against the ALM_MAG1 level averaged over the number of samples, as identified in the ALM_SMPL1 control register. This acts to create a comparison of ( units/ time) or the derivative of the output data variable against a predefined slope. The versatility built into the alarm function is intended to allow the user to adapt to a number of different applications. For example, in the case of monitoring a twos complement variable, Bit 15 within the ALM_MAG1 control register can allow for the detection of negative excursions below a fixed level. In addition, the Alarm 1 and Alarm 2 functions can be set to monitor the same variable that allows the user to discern if an output variable remains within a predefined window. Other options include the rate-of-change function that can be used in monitoring angular acceleration levels that would warrant special attention. With the addition of the alarm hardware functionality, the ADIS16250 can be left to run independently of the main processor and interrupt the system only when an alarm condition occurs. Conversely, the alarm condition can be monitored through the routine polling of any one of the five data output registers. The alarm hardware output indicator is not latched but tracks the actual alarm conditions in real time.
Preliminary Technical Data
MISCELLANEOUS CONTROL REGISTER
The MSC_CTRL control register within the ADIS16250 provides control of two miscellaneous functions: the data-ready hardware I/O function and the self-test function. The bits to control these two functions are shown in Table 27. The operation of the data-ready hardware I/O function is very similar to the alarm hardware I/O function (controlled through the ALM_CTRL control register). In this case, the MSC_CNTRL register can be used in setting up one of the two GPIO pins to serve as the hardware output pin that indicates when the sampling, conversion, and processing of the five data output variables has been completed. This register provides the ability to enable the data-ready hardware function and establish its polarity. The data-ready hardware I/O pin is reset automatically to an inactive state part way through the next conversion cycle, resulting in a pulse train with a duty cycle varying from ~15% to 35%, depending upon the sample period setting. Upon completion of the next sample/conversion/processing cycle, the data ready hardware I/O line is reasserted. The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control registers can influence the same GPIO pins. A priority level has been established to avoid conflicting assignments of the two GPIO pins. This priority level is defined as MSC_CTRL and has precedence over ALM_CTRL, which has precedence over GPIO_CTRL.
SAMPLE PERIOD CONTROL
The five output data variables within the ADIS16250 are sampled and updated at a rate based upon the SMPL_PRD control register. Note that the sample period given is defined as the cumulative time required to sample, process, and update all seven data output variables. The five data output variables are sampled as a group and in unison with one another. Whatever update rate is selected for one signal, all five output data variables are updated at the same rate whether they are monitored via the SPI or not. For a sample period setting of less than 15.62 ms (SMPL_RATE 0x07), the overall power dissipation in the part rises by approximately 300%. The default setting for the SMPL_RATE register is 0x01 at initial power-up, thus allowing for the maximum SPI clock rate of 2.5 MHz.
GENERAL PURPOSE I/O CONTROL
As previously noted, the ADIS16201 provides two generalpurpose, bidirectional I/O pins (GPIOs) that are available to the user for control of auxiliary circuits within the target application. All I/O pins are 5 V tolerant, meaning that the GPIOs support an input voltage of 5 V. All GPIO pins have an internal pull-up resistor of approximately 100 k, and their drive capability is 1.6 mA. The direction, as well as the logic level, can be controlled for these GPIO pins through the GPIO_CTRL control register, as defined in Table 47. These same GPIO pins are also controllable through the ALM_CTRL and MSC_CTRL control registers. The priority for these three control registers in controlling the two GPIO pins is MSC_CTRL has precedence over ALM_CTRL, which, in turn, has precedence over GPIO_CTRL.
SENSITIVITY/FILTERING CONTROL
The ADIS16250 offers three distinct sensitivity settings that result in the following measurement ranges: 320/sec, 160/sec, and 80/sec. It also has the ability to perform basic filtering on the five output data variables. Both of these functions are controlled and setup through the SENS/AVG control register. The filtering performed is that of a low-pass,
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Preliminary Technical Data
Bartlet-Window filter. The number of filter taps is determined through the SENS/AVG control register. The filtering applied through the SENS/AVG control register is applied to all five data output variables concurrently and, thus, one output variable cannot be filtered differently from another.
ADIS16250
register is broken into two bytes. The three lower bits of the lower data byte are used to indicate which error condition exists. The next two bits of the lower byte monitor the status of the maximum angular rate and the internal diagnostics. The two lower bits of the upper data byte are utilized in indicating which alarm condition exists.
POWER-DOWN CONTROL
The ADIS16250 has the ability to power down for user-defined amounts of time, using the SLP_CNT control register.
COMMAND CONTROL
The COMMAND control register is utilized in sending global commands to the ADIS16250 device. There are five separate commands that act as global commands in the controlling of the ADIS16250 operation. Any one of the four commands can be implemented by writing 1 to its corresponding bit location. The command control register has write-only capability and is volatile. Table 43 describes each of these global commands.
STATUS FEEDBACK
The status control register within the ADIS16250 is utilized in determining the present state of the device. The ability to monitor the device becomes necessary when and if the ADIS16250 has registered an alarm or error condition as indicated by the "alarm enable" within the five output data registers. The 16-bit status
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ADIS16250 PERIPHERALS
AUXILIARY ADC FUNCTION
The auxiliary ADC function integrates a standard 12-bit ADC into the ADIS16250 to digitize other system-level analog signals. The output of the ADC can be monitored through the AUX_ADC control register, as defined in Table 6. The ADC consists of a 12-bit successive approximation converter. The output data is presented in straight binary format with the fullscale range extending from 0 V to VREF. A high precision, low drift, factory calibrated 2.5 V reference is also provided. Figure 6 shows the equivalent circuit of the analog input structure of the ADC. The input capacitor, C1, is typically 4 pF and can be attributed to parasitic package capacitance. The two diodes provide ESD protection for the analog input. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This would cause these diodes to become forward-biased and start conducting. They can handle 10 mA without causing irreversible damage to the part. The resistor is a lumped component that represents the on resistance of the switches. The value of this resistance is typically 100 . Capacitor C2 represents the ADC sampling capacitor and is typically 16 pF.
VDD D C1 R1 C2
05462-038
Preliminary Technical Data
In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. When no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated.
AUXILIARY DAC FUNCTION
The auxiliary DAC function integrates a standard 12-bit DAC into the ADIS16201. The DAC output is buffered and fed offchip to allow for the control of miscellaneous system-level functions. Data is downloaded through the writing of two adjacent data bytes, as defined in its register definition. To prevent the DAC from transitioning through inadvertent states during data downloads, a single command is used to simultaneously latch both data bytes into the DAC after they have been written into the AUX_DAC control register. This command is implemented by writing 1 to Bit 2 of the command control register, which, once received, results in the DAC output transitioning to the desired state. The DAC output provides an output range of 0 V to 2.5 V. The DAC output buffer features a true rail-to-rail output stage. This means that, unloaded, the output is capable of reaching within 5 mV of ground. Moreover, the DAC's linearity performance (when driving a 5 k resistive load to ground) is good through the full transfer function, except for Code 0 to Code 100. Linearity degradation near ground is caused by saturation of the output amplifier. As the output is forced to sink more current, the nonlinear region at the bottom of the transfer function becomes larger. Larger current demands can significantly limit output voltage swing.
D
Figure 6. Equivalent Analog Input Circuit Conversion Phase: Switch Open Track Phase: Switch Closed
For AC applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins.
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Preliminary Technical Data REGISTER DETAILS
DATA OUTPUT REGISTER DEFINITIONS
Table 10. SUPPLY_OUT Register Definition
Address 0x03, 0x02
1
ADIS16250
Table 16. TEMP_OUT Register Definition
Access R Address 0x0D, 0x0C
1
Scale 1.8315 mV
1
Default N/A
Format Binary
Scale1 0.1453C
Default N/A
Format Twos complement
Access R
Scale is the weight of each LSB.
Scale is the weight of each LSB.
The SUPPLY_OUT register contains the sampled power supply measurements. A measurement of 0 V is equal to 0 LSBs. Table 11. SUPPLY_OUT Bit Designations
Bit 15 14 13,12 11:0 Description New Data Flag. Set when register data is updated. Error/Alarm. Set when error or alarm is activated. Not Used. Data Bits.
The TEMP_OUT register contains the digitized temperature data. A temperature of 25C ideally translates to 0x0000. Table 17. TEMP_OUT Bit Designations
Bit 15 14 13,12 11:0 Description New Data Flag. Set when register data is updated. Error/Alarm. Set when error or alarm is activated. Not Used. Data Bits.
Table 12. GYRO_OUT Register Definition
Address 0x05, 0x04
1
Scale1 0.07326/sec
Default N/A
Format Twos complement
Access R
Table 18. ANGL_OUT Register Definition
Address 0x0F, 0x0E
1
Scale1 0.03663
Default 0x0000
Format Binary
Access R
Scale is the weight of each LSB. This scale assumed 320/sec sensitivity setting.
Scale is the weight of each LSB.
With the range set to 320/sec, an angular rotation of 320/sec translates into 8736 LSB. A 0/sec rotational rate ideally translates to a value of 0x0000. Additional range settings of 160/sec and 80/sec are selectable with corresponding resolutions of 0.03663/sec/LSB (27.3 LSB//sec) and 0.018315/sec/LSB (54.6 LSB//sec) respectively. Theoretical full-scale range for the 320/sec, 160/sec, and 80/sec settings are 600/sec, 300/sec, and 150/sec respectively. Table 13. GYRO_OUT Bit Designations
Bit 15 14 13:0 Description New Data Flag. Set when register data is updated. Error/Alarm. Set when error or alarm is activated. Data Bits.
The ANGL_OUT provides integrated angular rate data, which represents relative angle. An output of 0x0000 translates to an angle of 0. Value can be reset to zero via the null command located within the COMMAND register. Register can also be overwritten with an arbitrary value between 0 and 359.963 with any subsequent integration of rotational data occurring relative to this value. Table 19. ANGL_OUT Bit Designations
Bit 15 14 13:0 Description New Data Flag. Set when register data is updated. Error/Alarm. Set when error or alarm is activated. Data Bits.
CALIBRATION REGISTER DEFINITIONS
Table 20. GYRO_OFF Register Definition
Address 0x11, 0x10
1
Table 14. AUX_ADC Register Definition
Address 0x0B, 0x0A
1
Scale 0.6105 mV
1
Default N/A
Format Binary
Access R
Scale1 0.018315/sec
Default 0x0000
Format Twos complement
Access R/W
Scale is the weight of each LSB.
Scale is the weight of each LSB.
The AUX_ADC register contains the digitized auxiliary ADC's output data. An input voltage of 0 V ideally translates into 0 LSBs. Table 15. AUX_ADC Bit Designations
Bit 15 14 13,12 11:0 Description New Data Flag. Set when register data is updated. Error/Alarm. Set when error or alarm is activated. Not Used. Data Bits.
The GYRO_OFF register is the user-controlled register for calibrating system-level angular rate offset errors. It represents the offset variable in the calibration equation (see the Calibration section). The maximum calibration range is 37.5/sec, or +2047/-2048 codes, assuming nominal sensor sensitivity. The contents of this register are nonvolatile and are set to zero upon initial power-up.
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ADIS16250
Table 21. GYRO_OFF Bit Designations
Bit 15:12 11:0 Description Not Used. Data Bits.
Preliminary Technical Data
The ALM_SMPL1 register contains the sample period information for Alarm 1, when it is set for rate-of-change alarm monitoring. The rate-of-change alarm function averages the change in the output variable over the specified number of samples and compares this change directly to the values specified in the ALM_MAG1 register. The contents of this register are nonvolatile. Table 27. ALM_SMPL1 Bit Designations
Bit 15:8 7:0 Description Not Used. Data Bits.
Table 22. GYRO_SCALE Register Definition
Address 0x13, 0x12
1
Scale1 0.0488%
Default 0x0800
Format Binary
Access R/W
Scale is the weight of each LSB.
The GYRO_SCALE register is the user-controlled register for calibrating system-level acceleration sensitivity errors. It represents the A variable in the calibration equation. This register offers a sensitivity calibration range of 0 to 1.9995, with unity gain being equal to 2048 LSBs. The contents of this register are nonvolatile. Table 23. GYRO_SCALE Bit Designations
Bit 15:12 11:0 Description Not Used. Data Bits.
Table 28. ALM_MAG2 Register Definition
Address 0x23, 0x22
1
Default1 0x0000
Format N/A
Access R/W
Default is valid only until the first register write cycle.
The ALM_MAG2 register contains the threshold level for Alarm 2. The contents of this register are nonvolatile. Table 29. ALM_MAG2 Bit Designations
Bit 15 Access R/W 14 13:0 Description Greater than active alarm bit. 1: Alarm is active for an output greater than Alarm Magnitude 2 Register setting. 0: Alarm is active for an output less than Alarm Magnitude 2 Register setting. Not Used. Data Bits. This number can be either twos complement or straight binary. The format is set by the value being monitored by this function.
ALARM REGISTER DEFINITIONS
Table 24. ALM_MAG1 Register Definition
Address 0x21, 0x20
1
Default1 0x0000
Format N/A
Default is valid only until the first register write cycle.
The ALM_MAG1 register contains the threshold level for Alarm 1. The contents of this register are nonvolatile. Table 25. ALM_MAG1 Bit Designations
Bit 15 Description Greater than active alarm bit. 1: Alarm is active for an output greater than Alarm Magnitude 1 Register setting. 0: Alarm is active for an output less than Alarm Magnitude 1 Register setting. Not Used. Data Bits. This number can be either twos complement or straight binary. The format is set by the value being monitored by this function.
Table 30. ALM_SMPL2 Register Definition
Address 0x27, 0x26
1
Default1 0x0000
Format Binary
Access R/W
Default is valid only until the first register write cycle.
14 13:0
Table 26. ALM_SMPL1 Register Definition
Address 0x25, 0x24
1
Default1 0x0000
Format Binary
Access R/W
The ALM_SMPL2 register contains the sample period information for Alarm 2, when it is set for rate-of-change alarm monitoring. The rate-of-change alarm function averages the change in the output variable over the specified number of samples and compares this change directly to the values specified in the ALM_MAG1 register. The contents of this register are nonvolatile. Table 31. ALM_SMPL2 Bit Designations
Bit 15:8 7:0 Description Not Used. Data Bits.
Default is valid only until the first register write cycle.
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Preliminary Technical Data
Table 32. ALM_CTRL Register Definition
Address 0x29, 0x28
1
ADIS16250
PROGRAMABLE FEATURE REGISTER DEFINITIONS
Access R/W
Default1 0x0000
Format N/A
Table 34. SMPL_PRD Register Definition
Address 0x37, 0x36
1
Default is valid only until the first register write cycle.
Default1 0x0001
Format N/A
Access R/W
The ALM_CTRL register contains the alarm control variables. Table 33. ALM_CTRL Bit Designations
Bit 15 Value Description Rate of Change (ROC) Enable for Alarm 2. 1: ROC is active. 0: ROC is inactive. Alarm 2 Source Selection. Alarm Disable. Alarm Source: Power Supply Output. Alarm 2 Source: Gyroscope Output. Alarm 2 Source: Inactive. Alarm 2 Source: Inactive. Alarm 2 Source: Auxiliary ADC Output. Alarm 2 Source: Temperature Sensor Output. Alarm 2 Source: Inactive. Rate of Change (ROC) Enable for Alarm 1. 1: ROC is active. 0: ROC is inactive. Alarm 1 Source Selection. Alarm Disable. Alarm Source: Power Supply Output. Alarm 1 Source: Gyroscope Output. Alarm 1 Source: Inactive. Alarm 1 Source: Inactive. Alarm 1 Source: Auxiliary ADC Output. Alarm 1 Source: Temperature Sensor Output. Alarm 1 Source: Inactive. Not Used. Data Source Select. This bit determines whether the Alarm thresholds are compared with pre-filtered data or post-filtered data. 1: Filtered data is used for alarm comparisons. 0: Pre-filtered data is used for the alarm comparisons Not Used. Alarm Output Enable. 1: Alarm output enabled. 0: Alarm output disabled. Alarm Output Polarity. 1: Active high. 0: Active low. Alarm Output Line Select. 1: DIO1. 0: DIO0.
Default is valid only until the first register write cycle.
The data within this register is nonvolatile, allowing for data recovery upon reset. The initial value is set to 0x01 upon initial power-up, allowing for a sample rate of 256 samples per second. Table 35. SMPL_PRD Bit Descriptions
Bit 15:8 7:0 Description Not Used. ADC Sample Period Count, ADC Sample Time Control Register. The 16 bit register is set to 0x01 upon initial power-up allowing for a combined sample rate of 256 samples per second (combined sample rate being the rate at which all four outputs are sampled and updated). The MSB, SR7, allows for selection of the combined base acquisition time of 1.953 ms with SR7 set to 0 ms or 60.54 ms when SR7 is set to 1. The lower seven bits, SR6 to SR0, represent a binary count, which when added to one and then multiplied by the combined base acquisition time, results in an overall acquisition time. Note that the minimal allowable setting for the bits SR6 to SR0 is 0x01. The overall acquisition time can be varied from 3.906 ms to 250 ms in 1.953 ms increments for SR7 = 0 and from 121 ms to 7.75 sec in 60.54 ms increments for SR7 = 1. This equates to the sample rate varying from 256 SPS to 4.0 SPS for SR7 = 0 and from 8.26 SPS to 0.129 SPS for SR1 = 1. Last written value is nonvolatile allowing for data recovery upon reset. Read/Write capability.
14:12 000 001 010 011 100 101 110 111 11
10:8 000 001 010 011 100 101 110 111 7:5 4
Table 36. SENS/AVG Register Definition
Address 0x39, 0x38
1
Default1 0x0402
Format Binary
Access R/W
Default is valid only until the first register write cycle.
The SENS/AVG controls two different features: sensitivity and averaging. The sensitivity directly impacts the measurement range of the sensor and the averaging setting establishes the number of taps in the filtering network.
3 2
1
0
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ADIS16250
Table 37. SENS/AVG Bit Description
Bit 15:11 10:8 Value Description Not used Sensitivity Selection Bits. Default setting: 320/sec. Suggest writing these three bits in a separate write command, before setting the average count using bits 3:0. 320/sec 160/sec; automatically limits AC2 to AC0 to 0x02 minimum. 80/sec; automatically limits AC2 to AC0 to 0x04 minimum. Not Used. The average count register represents the number of taps utilized within the digital filter. The 3-bit binary value identifies the number of taps as defined by 2N where N is represented by the binary data AC2 to AC0 and is limited to a value ranging from 0 to 7. The number of taps can thus be varied from 1 to 128 by powers of two. The register is set to 2 upon initial powerup resulting in an effective filter with a -3dB point of approximately 40 Hz (SMPL_PRD set to 256 SPS). The value within the average count register is applied concurrently to the primary output registers: gyroscope, power supply, sensor temperature, auxiliary ADC, and angle output. Minimum value written to these bits is superseded by the S2 to S0 bit setting. Last written value is nonvolatile allowing for data recovery upon reset. Read/Write capability. Address 0x3D, 0x3C
1
Preliminary Technical Data
Table 40. STATUS Register Definition
Default1 0x0000 Format N/A Access Read only
Default is valid only until the first register write cycle.
100 010 001 7:4 3:0
The STATUS control register contains the alarm/error flags that indicate abnormal operating conditions. See Table 41 for each status bit definition. Error flags are set as various error or alarm conditions occur, with the setting of multiple flags simultaneously being a possibility. Bits ST0, ST1, and ST4 are automatically cleared upon removal of the error condition thus making them "non-sticky." All flags are cleared upon the reading of the STATUS register. Potential exists for the flags to be set repeatedly if error conditions persist. All 0's upon reset. Read mode only. Table 41. STATUS Bit Descriptions
Bit 15:10 9 Description Not Used. Alarm 2 Status. 1: Active. 0: Normal mode. Alarm 1 Status. 1: Active. 0: Normal Mode. Not Used. Self-Test Diagnostic Error Flag. 1: Error Condition. 0: Normal Mode. Angular Rate Overrange. 1: Error Condition. 0: Normal Mode. SPI Communications Failure. 1: Error Condition. 0: Normal Mode. Control Register Update Failed. 1: Error Condition. 0: Normal Mode. Power Supply above 5.25 V. 1: Error Condition. 0: Normal Mode. Power Supply below 4.75 V. 1: Error Condition. 0: Normal Mode.
8
7:6 5
4
Table 38. SLP_CNT Register Definition
Address 0x3B, 0x3A
1
Default1 0x0000
Format Binary
Access R/W
3
Default is valid only until the first register write cycle.
The sleep count register is used in determining the duration of the sleep time within the sleep mode. The 8-bit register defines the sleep period by multiplying the binary value represented by SC7 to SC0 by the constant 0.5 sec. This results in a powerdown period varying from 0.5 sec to 127.5 sec in 0.5 sec increments. If the register reads 0, the sleep mode is disabled. The sleep count register is volatile and is set to all 0's upon initial power-up. At anytime during a SLEEP interval, the value 0x00 may be written to the SLP_CNT register in order to wake up the part. In addition, resetting the part prematurely wakes up the part from its sleep times. Table 39. SLP_CNT Bit Designations
Bit 15:8 7:0 Description Not Used. Data Bits.
2
1
0
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Preliminary Technical Data
Table 42. COMMAND Register Definition
Address 0x3F, 0x3E
1
ADIS16250
Table 45. MSC_CTRL Bit Descriptions
Access Write only Bit 15:11 10 Description Not Used. Internal Self-Test Enable. 1: Internal Self-Test Initiated. 0: Internal Self-Test Disabled. This bit initiates an internal diagnostics check of the sensor using simulated rotation rates relative to any steady state rotation. Once completed, the IST bit is cleared. Any errors are recorded in the STATUS register if detected. External Negative Self-Test Enable. 1: ENST Enabled. 0: ENST Disabled. Simulates negative angular rotation of ~ -50/sec relative to any steady state rotation. External Positive Self-Test Enable. 1: EPST Enabled. 0: EPST Disabled. Simulates positive angular rotation of ~50/sec relative to any steady state rotation. Not Used. Data-Ready Enable. 1: DR Enabled. 0: DR Disabled. Data-Ready Polarity. 1: Active High. 0: Active Low. Data-Ready Line Select. 1: DIO1. 0: DIO0.
Default 0x0000
1
Format N/A
Default is valid only until the first register write cycle.
The COMMAND control register is utilized in sending global commands to the ADIS16250 device. Table 43. COMMAND Bit Descriptions
Bit 15:8 7 6:4 3 Description Not used. Software Reset Command. Allows for resetting of the device via the SPI. Not used. Manual FLASH Update Command. Setting this bit high results in the nonvolatile registers being written to FLASH memory. The update process takes approximately 50 ms with the user being asked to refrain from using the SPI for 50 ms once the bit is set. Power should remain valid during this time. Also note that the NULL and FACTORY reset command bits also initiate the FLASH update process and require the same stipulations as does the manual FLASH update command bit. Auxiliary DAC Data Latch. This command latches any previous data sent to the auxiliary DAC registers into the DAC latches upon receipt of the command. This allows for sequential loading of the upper and lower DAC data bytes into the device via the serial interface without having the DAC go into unwanted states based upon the individual DAC bytes. Once the two bytes have been loaded, the DAC DATA latch command can be initiated to update the DAC. Factory Reset Command. Allows user to reset the system level GYRO_OFF and GYRO_SCL registers to the initial factory settings upon receipt of command. Data within the digital filters are reset as well. Also see CMD3 command. CMD0: Null Command. Sets the GYRO_OFF register upon receipt of command in order to zero out the Gyroscopic output. Also see CMD3 command.
9
8
7:3 2
2
1
0
1
Table 46. GPIO_CTRL Register Definition
Address 0x33, 0x32
1
Default1 0x0000
Format N/A
Access R/W
0
Default is valid only until the first register write cycle.
The data within auxiliary digital I/O control register is volatile and is set to 0s upon reset. Table 47. GPIO_CTRL Bit Descriptions
Bit 15:10 9 Description Not Used. General-Purpose I/O Line 0, Data Direction Control. 0: Input. 1: Output. General-Purpose I/O Line 1, Data Direction Control. 0: Input. 1: Output. Not used. General-Purpose I/O Line 0 Polarity. 0: Low. 1: High. General-Purpose I/O Line 1 Polarity. 0: Low. 1: High.
Table 44. MSC_CTRL Register Definition
Address 0x35, 0x34
1
Default1 0x0000
Format N/A
Access R/W
Default is valid only until the first register write cycle.
The 16 bit miscellaneous control register is used in the controlling of the self-test and data-ready hardware functions. This includes turning on and off the diagnostics feature and self-test functions, as well as enabling and configuring the dataready function. For the data-ready function, the written values are nonvolatile allowing for data recovery upon reset. The selftest data is volatile and is set to 0's upon reset.
8
7:2 1
0
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ADIS16250
Table 48. AUX_DAC Register Definition
Address 0x31, 0x30
1
Preliminary Technical Data
Table 49. AUX_DAC Bit Descriptions
Access R/W Bit 15:12 11:0 Description Not Used. Data Bits. Default 0x0000
1
Format Binary
Default is valid only until the first register write cycle.
The AUX_DAC register controls the ADIS16201 DAC function. The data bits provide a 12-bit binary format number with 0 representing 0 V and 0x0FFFh representing 2.5 V. The data within this register is volatile and is set to 0s upon reset. This register has read/write capability.
Rev. PrB | Page 22 of 28
Preliminary Technical Data APPLICATIONS
HARDWARE CONSIDERATIONS
The ADIS16250 can be operated from a single 5.0 V (4.75 V to 5.25 V) power supply. The ADIS16250 integrates two decoupling capacitors, 1 F and 0.1 F in value. For the local operation of the ADIS16250, no additional power supply decoupling capacitance is required. However, if the system power supply presents a substantial amount of noise, additional filtering can be required. If additional capacitors are required, connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should be noted that all analog and digital grounds be referenced to the same system ground reference point.
ADIS16250
not flow near analog circuitry and vice versa. The ADIS16250 can then be placed between the digital and analog sections. In all of these scenarios, and in more complicated real-life situations, keep in mind that the current flows from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Whenever possible, avoid large discontinuities in the ground plane as they force return signals to travel a longer path. Make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. If the user plans to connect any high speed logic signals (rise/fall times <5 ns) to either of the ADIS16250 digital I/O pins, add a series resistor to each line to keep the rise and fall times longer than 5 ns at the ADIS16250 digital I/O pins. A value of 100 or 200 is usually sufficient to prevent high speed signals from coupling (via parasitic capacitive paths) into the ADIS16250 and affecting the accuracy of the ADC conversions.
GROUNDING AND BOARD LAYOUT RECOMENDATIONS
As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADIS16250 designs in order to achieve optimum performance from the ADC and DAC. Understanding that the ADIS16250 typically connects to both analog and digital circuits, the user must tie the separate ground planes together very close to the ADIS16250. In systems where analog and digital ground planes are connected together somewhere else (at the system power supply for example), they cannot be tied together at the ADIS16250 since a ground loop would result. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do
BANDGAP REFERENCE
The ADIS16250 provides an on-chip band gap reference of 2.5 V, which is utilized by the on-board ADC and DAC. This internal reference also appears on the VREF pin. This reference can be connected to external circuits in the system. An external buffer would be required because of the low drive capability of the VREF output.
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ADIS16250
SECOND-LEVEL ASSEMBLY
The recommended pad geometries for the ADIS16250 are displayed in Figure 7. The ADIS16250 can be attached to printed circuit boards using SN63 (or equivalent) or lead-free solder. Figure 8 and Table 50 provide recommended solder reflow profiles for each solder type. Note: These profiles may not be the optimum profile for the user's application. In no case, should the temperature exceed 260C. It is recommended that the user develop a reflow profile based upon the specific application. In general, keep in mind that the lowest peak temperature and shortest dwell time above the melt temperature of the solder results in less shock and stress to the product. In addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly. Table 50.
Preliminary Technical Data
Condition Sn63/Pb37 Pb-Free 3C/sec max 3C/sec max 100C 150C 60 sec to 120 sec 3C/sec 150C 200C 60 sec to 150 sec 3C/sec
Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (ts) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tp) Ramp-Down Rate Time 25C to Peak Temperature
183C 60 sec to 150 sec 240C + 0C/-5C 10 sec to 30 sec 6C/sec max 6 min max
217C 60 sec to 150 sec 260C + 0C/-5C 20 sec to 40 sec 6C/sec max 8 min max
TP RAMP-UP
TEMPERATURE
tP
CRITICAL ZONE TL TO TP
TL
TSMAX TSMIN
tL
tS
PREHEAT
RAMP-DOWN
05462-042
t25C TO PEAK
TIME
Figure 7. Recommended Pad Layout
Figure 8. Acceptable Solder Reflow Profiles
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Preliminary Technical Data OUTLINE DIMENSIONS
ADIS16250
Figure 9. 20-Terminal Land Grid Array [LGA] (CC-20-5) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16250ACCZ ADIS16250/PCBZ Temperature Range -40C to +85C Package Description 20-Terminal Land Grid Array [LGA] Evaluation Board Package Option CC-20-5
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ADIS16250
Preliminary Technical Data
NOTES
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Preliminary Technical Data
ADIS16250
NOTES
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ADIS16250
Preliminary Technical Data
NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06070-0-6/06(PrB)
T T
Rev. PrB | Page 28 of 28

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